As semiconductors have become more highly integrated, the number of input-output terminals has increased. Accordingly, semiconductor packages having a large number of input-output terminals have become required. Input-output terminals are commonly grouped into a type where the terminals are arranged in a line on the perimeter of a semiconductor package and a type where they are arranged in lines not only on the perimeter but also in the inner area of a semiconductor package.
The former is typified by QFP (quad flat package). To make it have more terminals, terminal pitches must be made narrower. However, in a region of 0.5 mm pitch or less, a high-grade technique is required to connect terminals to a wiring board.
The latter array type enables arrangement of terminals at relatively large pitches, and hence is suited for multipin construction. As the array type, PGA (pin grid array), having connecting pins, has commonly been available. This, however, is of an insert type for its connection with a wiring board, and is not suited for face packaging. Accordingly, a package called BGA (ball grid array), which enables face packaging, has been developed.
Meanwhile, as electronic instruments are made compact, there is a stronger demand for making package size smaller. As a package that meets such a demand for smaller size, what is called a chip-size package (CSP) is proposed. This is a package having portions connecting with an external wiring substrate, not on the perimeter of a semiconductor chip but in its packaging region. As specific examples, it includes those in which a polyimide film with bumps is bonded to the surface of a semiconductor chip so as to make electrical interconnection with the chip through gold lead wires, followed by potting of epoxy resin or the like to effect encapsulating (NIKKEI MATERIALS & TECHNOLOGY 94.4, No. 140, pp.18-19), and those in which metal bumps are formed at positions corresponding to portions where a semiconductor chip connects with an external wiring substrate, and the semiconductor chip is face-down bonded, followed by transfer molding on a provisional substrate (Smallest Flip-chip-like Package CSP; The Second VLSI Packaging Workshop of Japan, pp.46-50, 1994).
However, it does not mean that most semiconductor packages hitherto proposed are small-sized and adaptable to high integration and also to be preventive of package cracking and have a superior reliability and yet to have a superior productivity.